VHDL code for the shifter will be presented together with its testbench VHDL code for functional simulation. The input/ output interface of the shifter is shown in the above figure. The shifter instruction set is as follows: SHIFTCtrl = '1000': SHIFTOUT 8. SHIFTCtrl = '1001': SHIFTOUT 4. Universal Shift Register. Write a verilog module to implement a negative edge triggered D flip-flop as follows: module dff (q, d, clk); input d, clk.

• VERILOG CODE

module univcount (Resetn,Clock,Q,modsel);
input Resetn,Clock,modsel;
output[3:0] Q;
reg [3:0] Q;
always@(posedge Clock)
if (!Resetn)
Q <= 0;
else if (modsel 0)
begin
if (Q 4’b1111)
Q <= 4’b0000;
else
Q <= Q + 1;
end

else
begin
if (Q 4’b0000)
Q <= 4’b1111;
else
Q <= Q – 1;
end

endmodule

• TEST BENCH FOR 4 BIT UNIVERSAL COUNTER

module univcounttstbnch;
reg rst,modsel,clk;
wire [3:0]q;
univcount cnt (rst,clk,q,modsel);

initial
begin
clk=0;
rst = 0;
modsel= 0;

$monitor($time, ,”c=%b”,clk, ,”r=%b”,rst, ,”M=%b”,modsel, ,”q=%b”,q);
#3 rst=1;
#9 modsel=0;
#23 modsel = 1;

end

always #1 clk = ~clk;
initial #69 $finish; Crack datamine studio 3.

endmodule